Conventional approaches typically test a chip after fabrication. High testability can be achieved by merging the design and test processes. One conventional testing technique is a scan design. Conventional scan design circuitry implements a serial connection of the various storage elements of a design into a scan chain. The process for inserting scan circuitry into the design involves replacing sequential elements with scannable sequential elements, and then stitching them into one or more scan registers (scan chains). The scan chain is the mechanism for shifting data in and out of the design through the primary inputs and outputs. The scan shifting operation is controlled by a scan enable pin. Shifting data into the chip puts the sequential elements in a known state. Operating the circuit with that known data, and capturing the output, allows the results to be observed and compared with expected data.
Shifting data in and out of the chain is done during a “shift mode”. The operation of the circuit and capturing the data is done during a “capture mode”. In the capture mode, a scan enable signal is in a non-active level, so the functional paths of the design are valid. A pulse on one or more scan clock ports is given to capture the data. A user controls how many capture clock pulses are supplied by the ATPG tool while the chip is in the capture mode. The capture mode is followed by the shift mode, and the data is shifted out and compared with expected data.
An automatic test pattern generation (ATPG) tool may be used to generate patterns to test the functionality of the chip. The ATPG tool configures the chip to be in shift mode or capture mode as needed. The patterns include data that are driven into the chip using the scan ports as well as the primary inputs. Pulses are also driven using the scan clock ports. The ATPG tool also generates expected data that is compared with the data that the chip outputs at specific times.
For verification purposes, it is important to ensure that there are no timing violations in either of the modes in order to ensure proper operation of the scan circuitry and to observe correct data. Therefore, a static timing analysis tool should be run, and setup and hold violations should be fixed. To avoid clock skew issues between clocks trees, the ATPG tool typically generates capture pulses one at a time. Analyzing the timing of non-simultaneously toggled clocks using an STA tool that normally analyzes multiple clocks as simultaneously clocked may result in false path violations being reported.
It would be desirable to implement a method and/or apparatus that (i) checks the timing of a chip while in scan mode, (ii) takes into account the non-simultaneous relations of multiple clocks in ATPG-generated vectors, and/or (iii) avoids reporting timing violations that may be falsely reported based on the special timing of the clock signals that are supplied to the chip.